Lead Analog Layout Engineer

Description

An exciting High-Tech scale-up revolutionizing wired connectivity seeks a Lead Analog Layout Engineer to join their talented team. A generous salary will be offered up to CGBP75K with Hybrid working.

The Lead Analog Layout Engineer will possess a background in Semiconductor physics, a strong academic history and proven experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits.

You ll take responsibility for the custom layout and verification of analog circuits, cells, blocks and IP for multi-gigabit high speed chip to chip communication links in advanced semiconductor technology nodes as well as supporting IP and chip level integration.

Your skills and experience should include:

Minimum of a Bachelors Degree in Electronic Engineering or similar. Proven experience in layout of high-speed circuits like amplifiers, oscillators or delay-locked loops. Knowledge of fundamental building blocks such as buffers, biasing, regulators or filters. Expertise in custom analog layout of circuits and blocks for Multi-Gigabit serial data-link transceivers or HF/RF circuits. Using EDA tools for design and verification such as Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, DRC/LVS. A background in Semiconductor Physics. This role can be based in either Berkshire, UK or in Switzerland. Hybrid model available and generous benefits package.

Ad ID: 5417757372